1. Field of the Invention
This invention relates generally to planarization in a chemical mechanical polishing process, and more particularly to in-situ monitoring of removal rate and thickness of a top layer during planarization.
2. Description of the Related Art
The semiconductor industry is continually striving to improve the performance of semiconductor devices, while still attempting to reduce the cost of these same devices. These objectives have been successfully addressed by the ability of the semiconductor industry to practice micro-miniaturization, or to fabricate semiconductor devices with sub-micron features. Several fabrication disciplines, such as photolithography, as well as dry etching, have allowed micro-miniaturization to be realized. The use of more sophisticated exposure cameras, as well as the use of more sensitive photoresist films, have allowed the attainment of sub-micron images in photoresist films, to be routinely achieved. In addition, the development of more advanced dry etching tools and processes, have allowed the sub-micron images, in masking photoresist films, to be successfully transferred to underlying materials used for the fabrication of semiconductor devices.
Integrated circuits are chemically and physically integrated onto a substrate, such as a silicon substrate, by patterning conductive regions in the substrate and by patterning conductive and insulation layers over the substrate. The various conductive and insulation layer create uneven surfaces on a semiconductor structure. Interlevel dielectric (ILD) layers are formed between conductive layers (e.g., metal or polysilicon) in a semiconductor device or between conductive lines formed from the same conductive layer (in the same level). Contact holes are formed through the ILD layers to make electrical contact with conductive layers and device regions there below. A typical ILD stack of oxides is shown with reference to FIG. 1.
FIG. 1 is a diagram showing a prior art ILD based structure 100. The prior art ILD based structure 100 includes a first oxide layer 102 upon which a metal line 104 has been formed. Over these is formed a first film of conformal oxide 106. The first conformal oxide film 106 typically is formed using a plasma enhanced chemical vapor deposition (PECVD) process in order to deposit the film 106 such that it conforms to the topography on the surface of the wafer.
A second oxide film 108, which is also highly conformal, is deposited over the first conformal film 106 to fill any gaps between the metal lines 104. A cap-oxide layer 110, which is thicker than the other oxide layers, is deposited over the second oxide film 108. During a chemical mechanical polishing (CMP) process, most of the cap-oxide layer is removed or polished away. In particular, the process control is required to monitor the thickness of the cap-layer 110 and stop the CMP process at a predefined thickness.
In view of the foregoing, there is a need for systems and methods for efficiently polishing oxide layers during ILD CMP processes. The methods should provide fast and efficient removal of the cap-oxide layer to a predetermined thickness.
Broadly speaking, the present invention fills these needs by providing a two step polishing process having fast and slow removal rates, respectively. To increase accuracy during the first portion of the polishing process, embodiments of the present invention provide in-situ monitoring of the removal rate and thickness of a top wafer layer during planarization. In one embodiment, a method is disclosed for removing a top wafer layer during a CMP process. Time series data is collected based on a reflected wavelength from a top layer of a wafer. A frequency of peak intensities in the time series data is used to determine a removal rate of the top layer, and the removal rate is used to calculate a current thickness of the top layer. The CMP process is discontinued when the current thickness of the top layer is equal to or less than a target thickness, and a separate polishing process is performed to remove an additional portion of the top layer. The frequency can be determined by applying a Fourier Transform to the time series data. The Fourier Transform of the time series data can be analyzed to determine a peak magnitude in the frequency, which corresponds to the frequency of peak intensities in the time series data. The removal rate for top layer can be calculated based on the peak magnitude in the frequency, which can be used to calculate the current thickness of the top layer.
In another embodiment, a system is disclosed for removing a top wafer layer during a CMP process. The system includes a light source for illuminating a top layer of a wafer, and an optical detector for collecting time series data based on a reflected wavelength from the top layer. Further included in the system is logic that determines a removal rate of the top layer based on a frequency of peak intensities in the time series data, and logic that calculates a current thickness of top layer based on the removal rate. A process controller is also included that discontinues the CMP process when the current thickness of the top layer is equal to or less than a target thickness. Optionally, the system can include an endpoint detection subsystem that performs a separate polishing process to remove an additional portion of the top layer. As above, the logic can apply a Fourier Transform to the time series data to determine the frequency, which can be analyzed by addition logic to calculate a removal rate for top layer based on a peak magnitude in the frequency.